Static random access memories designed as integrated circuits require increasingly shorter access times to stay commercially competitive. Shorter access times present difficulties, however. The memory blocks inside the integrated circuit are laid out in repeated cell structures, which conveniently use common lines for data inputs and outputs, which can present a difficulty in that even though these lines are metal, they act as transmission lines with significant resistance and parasitic capacitance. These long lines create large time constants for signals to reach their steady-state values and limit how fast the memory can be accessed. The high resistance also causes significant voltage differences in data signals between the case in which a memory block located at one end of the transmission line is accessed and the case in which a memory block at the other end is accessed, making the data signals more difficult to sense.